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In the $60bn NAND tech market, patent landscape analysis can give companies the edge, as Martin Bijman and Trevor Izsak of TechInsights explain.
In digital electronics, a NAND (NOT-AND) gate is an electronic circuit whose output is false only when both of the inputs are true. Otherwise, the output is true. In NAND memory, the respective inputs are stacked memory elements.
The NAND market is built on constantly-advancing innovations, many of which can be revealed using reverse engineering analysis to support both competitive intelligence and IP goals.
"Samsung released the first 3D NAND product in 2013, which consisted of 24 layers. Today the leaders either have released, or will shortly release, 96-layer products."
This article will discuss the different types of advanced technical analysis that are regularly prepared in response to disruptive events in NAND memory, the landscape of companies and patents that support NAND, and example methodologies used to identify, prioritise, and leverage patents of value relative to these technologies.
NAND memory is the second largest integrated circuit (IC) product category today, with over $60 billion in revenue in 2018, representing an increase of 18% over 2017. This growth was fuelled by a higher average selling price, growing use of solid-state drives in data centre server storage, and larger memory capacity in smartphones.
While the market is large, the number of NAND manufacturers is quite small, with the top six capturing over 99% of the market. This exclusivity is due to the enormous capital investment required each year to stay competitive in this market. Capital expenditures for non-volatile/flash memory were over $30 billion in 2018 alone. While the NAND market is currently dominated by Samsung, Toshiba Memory, Western Digital, Micron, SK Hynix and Intel, we also see significant investment from Chinese vendors such as YMTC.
As NAND technology advances, the patent landscape changes. Some industry leaders have executed cross-licensing agreements and created joint ventures and partnerships to move forward, but now we are seeing Chinese players such as YMTC filing 3D NAND patents, which further complicates the
TechInsights has been monitoring the NAND market for decades through its reverse engineering, technology analysis, and patent portfolio analysis activities. NAND innovation continues to aggressively boost memory density while lowering the price per bit. This evolution of innovation started with conventional two-dimensional planar NAND architectures with density improvements coming from smaller process nodes.
Improving density in this manner became more difficult with each successive generation, leading to 3D (vertical) NAND, where the memory arrays are fabricated in layers.
Samsung released the first 3D NAND product in 2013, which consisted of 24 layers. Today the leaders either have released, or will shortly release, 96-layer products. Adding layers increases the complexity of manufacturability and can cause yield issues. While manufacturers advance the number of layers (128-layer is expected in the second half of 2019), other strategies are being used for density improvements.
Memory cells which originally stored a single bit are now typically triple-level-cells (TLC), meaning they can store three bits per cell. In mid-2018, for example, the Intel/Micron NAND joint venture, IM Flash, released quad-level-cell technology (QLC) providing a 33% density improvement over TLC.
Innovation, IP and reverse engineering
In addition to the semiconductor innovations, numerous technologies are involved in the reliable operation of NAND in a product. Therefore, for each new technology event, many companies are interested in understanding what existing technologies are still being used, as well as what new technologies have been added, as this will impact their IP strategy.
One way to determine what and where NAND technologies are being used is through reverse engineering. The types of reverse engineering required to support NAND arguments can take on many forms and target a wide variety of leading-edge features:
Software and protocols associated with the physical interfaces and communication between a host to a memory controller, and from the memory controller to the NAND device.
Waveforms associated with internal communication within the NAND device, and characterisation of the memory cell.
Packaging innovations including materials used to ensure reliability. The assembly of the latest 64-layer NAND products has been observed to avoid state-of-the-art packaging solutions in favour of established, low cost, low pin count wire bond.
Semiconductor fabrication front-end-of-line: technologies and processes that result in the fabrication of the individual complementary metal-oxide semiconductor (CMOS) elements on the wafer. This includes wafer development, lithography, deposition, etching, and doping.
Semiconductor fabrication back-end-of-line: technologies and processes that provide the metal interconnection (metallisation) between the on-die elements.
To understand where companies have IP strength in the NAND market, a landscape can indicate the quantity of the full range of technologies used to create NAND. This enables a comparison of a company’s holdings to others in the market, which can identify over-patenting, ‘white space’ (little or no patenting) and opportunities for patent enforcement.
A landscape of flash patents is shown in Figure 1. It separates into four areas: (i) oxide-nitride-oxide (ONO) technologies used in early implementations of making stacked memory elements; (ii) structures, which includes the more recent 3D layer stacks; (iii) connectivity, at both the cell level and top level of a device; and (iv) circuits, which includes sense (memory reading) and programming (memory writing).
The landscape includes IP from more than 250 organisations, the top 40 of which are included in Figure 2, which provides an indication of flash-related patent counts. Flash memory retains data in the absence of a power supply, and NAND memory is one kind of flash memory. This suggests there is a broad range of organisations that may have IP
that may be applicable to NAND devices. Each company may have strengths in various areas of the landscape and may include IP that was developed for other flash applications that may be leveraged regarding NAND products.
Developing evidence of use
Typically, the information gathered through the reverse engineering is mapped to specific patent claims elements, which together form the argument required to enforce patents. This requires finding patents that enable technologies of the most economically important features of infringing products and using existing and new evidence gathered through reverse engineering.
For a company wishing to enforce their patents, there are four steps to developing evidence of use:
- Research the target company’s revenue and determine the economically important features within the products in each line of business. Determine what existing evidence is available describing the features, including both publications and existing reverse engineering.
- Mine your portfolio and the market for candidate patents that enable these important features. This may include sorting your patents into clusters, prioritising which patents to read first based on existing evidence and engineering capability to create more evidence, and reviewing these vetted patents to identify those with the highest potential for evidence of use.
- Create new reverse engineering to support elements of the best candidate patents.
- Analyse and refine the reverse engineering to develop evidence to show that all the interpreted claim elements are practised.
One key area of research in NAND is process integration as more layers are added. Additional layers cause stress and warping of the stack structure. Reducing the sense current through this stack is needed to improve reliability. New innovations are emerging to make the structure of the gate stack more vertical and uniform, therefore narrowing the height of each layer. This improves the alignment of the gate stack, enables a reduction in the channel sense current, and enables adding more layers.
An IP landscape may be used to help mine not only patents within your portfolio, but also patents for potential purchase that may be applicable to this emerging technology. Analysis of today’s landscape revealed several candidate patents regarding ‘three-dimension channel current’. These seed patents can be used to find other patents that are semantically similar for potential investigation.
Reverse engineering of high-volume products on the market could then be pursued to support the claim elements of candidate patents. Most often, more than a dozen highly-rated candidate patents are identified that target each technical area of the products in order to improve the likelihood of success that at least one evidence of use document is developed.
As NAND technology evolves, the strategies of companies with NAND-related IP must also evolve. Practically speaking, NAND innovation impacts every facet of the NAND ecosystem, from key industry players and patent holders, to manufacturing methods and memory density, to price per bit.
Further, reverse engineering capabilities for finding relevant evidence of use requires
continuous development in this rapidly advancing technology space.
A successful IP strategy in this field requires an awareness of disruptive events in NAND, knowledge of key and upcoming market players, and the correct application of reverse engineering techniques to identify the changes from generation to generation of the latest NAND technology.
Martin Bijman is director, IP products at TechInsights. He can be contacted at: email@example.com
Trevor Izsak is a director, product management at TechInsights. He can be contacted at: firstname.lastname@example.org
NAND technology, TechInsights, digital electronics, innovation, integrated circuit, capital investment, Samsung, Toshiba, Intel, patent landscape