Two lines of attack: protecting semiconductors in India
Semiconductors have played a major role in the growth of technology over the last few decades. The powerhouse behind the growth was undoubtedly progress in integrated circuits (IC) technology. The IC is an integral part of every computer chip. Cutting-edge fifth and sixth generation computers are now using very large scale integration (VLSI), wherein numerous transistors are accommodated on a single chip.
India has become a hub for semiconductor design, with nearly 2,000 chips being designed per year and more than 20,000 engineers working in various aspects of chip design and verification. India’s semiconductor consumption has reached $8 billion in 2012, a 7.4 per cent increase from 2011. It is expected to reach $9.6 billion in 2013. The various industries using semiconductor technology in India are wireless handsets, communications, information technology (IT) and office automation.
Laws protecting ICs
In India semiconductor ICs and layout designs are protected under the Semiconductor ICs Layout-Design (SICLD) Act, 2000. The Indian Patents Act excludes patenting of topography of ICs and layout designs in view of Section 3(o) of the Patents Act.
The SICLD Act defines the following terms:
Semiconductor IC: A product with transistors or other circuitry elements which are inseparably formed on a semiconductor material or an insulating material or inside the semiconductor material and designed to perform an electronic circuitry function.
Layout design: A layout of transistors and other circuitry elements including lead wires connecting such elements and expressed in any manner in a semiconductor IC.
As per the TRIPS Agreement, ‘layout design’ is synonymous with ‘topography’. A layout design is defined as the three-dimensional disposition, however expressed, of the elements, at least one of which is an active element, and of some or all of the interconnections of an IC, or such a three-dimensional disposition prepared for an IC intended for manufacture.
Protection under the SICLD Act
A layout design expressed in any original manner which is inherently distinctive and capable of being distinguishable from any other registered layout design, and which has not been commercially exploited for more than two years from the date of application for the registration, is protected or registered under the act.
Decisions related to Section 3(o)
Patent application 1231/MAS/1999 titled ‘IC of inductive elements’ claimed an IC. The controller raised an objection that the claims of the application fell within the scope of Section 3(o) of the Patents Act. The applicant in reply to the objection in the First Examination Report (FER) submitted that the inventive feature of the application lay in the screening means for insulating the active region in the form of an automatic field. The applicant stated that this inventive feature cannot be considered as a mere topography of ICs. In view of the response the controller granted a patent for the application.
Likewise, patent application 3521/DELNP/2005 titled ‘Multi-die semiconductor package’ claimed a semiconductor package. The applicant in reply to the objection under Section 3(o) submitted that the application related to a semiconductor package and a method of manufacturing the same. This cannot be considered as topography of ICs, the applicant said, and therefore the patent was granted for the application.
In a recent decision on patent application 2027/MUM/2006, the Indian Patent Office granted a patent for a method for macro placement of a semiconductor chip, notwithstanding an objection under Section 3(o) of the Patents Act. One of the main non-procedural objections to the claims as voiced by the examiner was that the claims fell under the Section 3(o) prohibition, since they defined the topography of ICs.
The applicant argued that the amended claims do not direct towards the fabrication process step and in turn to the layout design of the IC. The controller held that the claims are directed towards the concept and methodology of integration of macros used in the design of ICs and in turn direct to physical design step. Further the controller stated that the application resolves the conceptual and design issues relative to area, speed, data path, power characteristics and distribution of the design.
Consequently the patent was granted, since the subject matter didn’t attract the provision of Section 3(o) of the Patents Act.
"The application related to a semiconductor package and a method of manufacturing the same. This cannot be considered as topography of ICS, the applicant said, and the patent was granted."
Indian legislation provides comprehensive protection to semiconductor technology. Topography of ICs and layout designs is protected under the SICLD Act and subject matter other than that protected under SICLD Act can be a patentable subject matter under the Indian Patents Act.
Presently, semiconductor companies are apprehensive that inventions related to semiconductors cannot be patented in view of Section 3(o) of the Patents Act, which excludes patenting topography of ICs. After differentiating the subject matter related to semiconductor ICs falling under the SICLD Act, one can infer that only a small part of the subject matter of ICs is protected under the SICLD Act. The Patents Act provides protection for the major part of the subject matter which is not protected under SICLD Act.
Semiconductor companies could protect their IP by filing patent applications in India for the subject matter of semiconductors which include ICs and layout design such as chips as a product, semi-product, technology used in production of topographies or ICs, application or functionality of the IC, information or data present within an IC, processes, systems, methods, formation of semiconductor product, etc.
Topography of ICs and layout designs can be registered under the SICLD Act providing complete protection to the functionality as well as design aspects of semiconductor ICs.
Afsar S is an advocate, patent attorney and a partner with Krishna & Saurastri Associates. He can be contacted at afsar@krishnaandsaurastri.com.
Chinthan Japhet is a patent consultant in the engineering department of Krishna and Saurastri Associates. He can be contacted at
chinthan@krishnaandsaurastri.com.
