Assessing the evidence: semiconductor portfolio management

18-04-2018

Martin Bijman

Assessing the evidence: semiconductor portfolio management

gorodenkoff / iStockphoto.com

If you are not examining the patents in your semiconductor portfolio for which evidence of use is harder to prove, you are not leveraging your full portfolio, says Martin Bijman of TechInsights.

 Patent licensing is an established and accepted part of the semiconductor industry; companies renew licences for their innovations with others in the industry and leverage these innovations regarding products in original equipment manufacturer (OEM) markets.

Licensing and leveraging rely, in part, on being able to provide evidence of use (EoU) of innovations. Portfolio owners are generally more inclined to pursue EoU where it is easier to do so. In our experience, a third of the patents in a portfolio are easier to develop EoU with established practices, and clients readily leverage these patents.

In the semiconductor industry, however, the remaining two-thirds of the patents within any portfolio will be harder to develop EoU for—and the return on investment associated with these patents can be significant. In TechInsights’ decades of experience in analysing patents, and in reverse engineering technology in support of patent activities, we have found that 14% of the EoU we have developed was in support of patents where it was harder to prove EoU.

If you are not examining the patents in your portfolio that are harder to prove EoU for, you are not leveraging your full semiconductor portfolio.

Semiconductor patent types

From an EoU standpoint, semiconductor innovations can be sorted by the approach used to prove their use:

Process: related to producing semiconductor die. This includes:

  • Materials patents, where EoU reads on the chemistry profiles used to make semiconductor wafers; and
  • Structure patents and layout patents, where topographic images can reveal innovations in cell library devices and die interaction.
  • Packaging: where EoU is gathered using microscopes, X-rays, and materials analysis to capture images of semiconductor die, die stacks, connectivity, and encapsulation.
  • Circuit: where scanning electron microscope (SEM) image arrays and software tools help analysts trace and organise electrical connectivity among structures at the die, package, module, or printed circuit board (PCB) level.
  • Systems: where EoU is gathered through literature review, physical and electrical measurement, packet sniffing, addressing security mechanisms, and observation of an electronic product while in operation.
  • Software: where EoU is gathered through source code review, device driver analysis, and through extraction of machine code which may be disassembled, structured, and then operated to observe behaviour and data flow.

 Figure 1Figure 2

 

How much EoU is harder to prove?

Figure 1 shows a sampling of semiconductor patents that TechInsights has successfully documented with EoU. This landscape shows that a wide variety of technologies can be successfully documented regarding semiconductors.

Figure 2 highlights patents from Figure 1 where it was harder to prove EoU. This landscape shows that many aspects to the implementation of innovations can make it challenging to prove use, yet it can be done successfully.

What makes EoU more difficult to prove?

Many factors can make gathering EoU more difficult, such as:

  • Ability to procure or get access to the product of interest;
  • The amount of residual evidence of the innovation present in the final product;
  • Challenges to reverse engineering;
  • The investigation can be exceedingly expensive and time-consuming; and
  • Claim limitations.

To provide some perspective on what makes it harder to prove that an innovation is used, let’s consider some examples in each of the five areas.

Figure 3 Figure 4 

Process innovations

Process EoU is typically very economical. The standard approach to create EoU is to depopulate a semiconductor die from an encapsulated package, and create images from the top or side. From the top, the die may be delayered to expose the target structure, which is then imaged optically, or SEM imaged. From the side, the die is cleaved to expose a cross section in the area of interest, which is imaged using SEM or scanning capacitance microscopy (SCM) techniques. EoU is created by mapping claim elements to these images.

Some process patents are virtually unprovable, where there is no residual of the innovation; for example, steps in the semiconductor manufacturing process.

Challenging patents requires deeper analysis that incurs higher cost, yet has a high rate of success. This may include materials analysis, transmission electron microscope (TEM) sample prep and imaging, and investigation of doping profiles. New techniques and imaging are continually developed as process node sizes drop, analysing structures on glass, air gaps, die stacks, 3D process for example used in 3D NAND, and new implementations using nanotechnology and optics.

Packaging innovations

Packaging EoU is also typically very economical. The approach starts with X-ray, the mechanical preparation of a sample to obtain a cross section in the area of interest, which is then optically imaged.

Some method claims about packaging innovations can be implied by examining the final product, but there may be no residual. There are cases when literature can be found that complements EoU.

Challenging packaging patents may require more time and cost to prove use, yet are quite achievable. Examples include:

  • Materials analysis using SEM/energy-dispersive spectroscopy (EDS);
  • Delayering a package to create a schematic of connectivity, or to support shielding of interconnect within a package; and
  • Using 3D X-ray for some investigations.

Figure 5  Figure 6

Circuit innovations

Circuit EoU that is based on fully organised schematics can be expensive, whereas EoU based on high-level analogue block architectures can be more economical and quicker to prepare. Circuit schematics are created by delayering and SEM imaging each layer of die connectivity and vertical interconnect access (VIAs), stitching the mosaics of images into tools, which are analysed into hierarchical schematics.

Block-level architectures can be created using only a subset of these layers, where an analyst determines the function of each block in the chain without doing full schematic extraction.

Creating full schematics of Systems on chip (SoC), digital cores, and field-programmable gate arrays (FPGAs) is achievable but expensive, and are not often pursued for circuit EoU.

There are many examples of circuit investigations that are more challenging:

  • Older process technologies can create higher difficulty when delayering samples;
  • Circuits that involve both analogue and digital logic can be challenging, unless the digital is localised rather than included within a large sea of gates;
  • Innovations that reference specific numbers and ranges of voltage and current are challenging, they may require deeper analysis of circuit constraints, or simulation of their operation, which adds the requirement of finding device models for the process node; and
  • Some innovations use unique device structures that may need to be modelled, or operate devices in subthreshold mode for example to save power.

Systems innovations

Obtaining systems EoU can include a wide range of effort, as systems cover such a wide range of technologies. Typically, EoU is developed by looking at a target, taking it apart, or turning it on. Evidence may include literature, physical inspection, re-creating operation as experienced by the end user, or deep analysis of the internal operations.

Some systems patents are virtually unsupportable. Examples include the inability to procure or access the target, or to provision it into its normal operating mode. It is hard to buy a wireless base station, or a module used in expensive medical equipment. It is difficult to get access to cloud deployments, or to the secure contents of SoC memory, or an FPGA configuration. It is difficult to simulate the machine learning algorithm of internet of things analytics, or the operation of an automobile in road conditions.

Some systems investigations are achievable with imaginative approaches, method experimentation, and refinement:

  • Functional testing of semiconductor circuits can be achieved with electrical probing and microsurgery;
  • OEM development kits can be procured, which give access to the inner workings of products and semiconductors;
  • Packet traffic can be sniffed;
  • Wireless traffic can be simulated to create examples of the desired conditions to demonstrate an innovation;
  • Printed circuit boards can be reverse engineered; and
  • The behaviour of applications implemented in the cloud can be observed in response to a specific sequence of network traffic.

 Figure 7 

Software innovations

Software inventions are relatively economical when investigating source code or drivers; it is much harder for embedded software or locked products, yet can be achieved with a methodical approach.

Software patents that may be virtually unsupportable are those in inaccessible systems, such as those in the cloud, or those in complex obfuscated devices, such as FPGAs.

Examples of harder yet achievable proof of software innovations involves the investigation of embedded software, and products protected by security layers. For embedded, the planned approach includes getting access to a test port, then the processor, then the memory contents, decompiling into structured software, find the code of interest, determine functionality, and thus the dataflow. For products protected by security, skilled analysts with knowledge of workarounds and creative approaches can often gain access to phones, memories, encryption, and other lockouts.

Why pursue the hard stuff?

While it may be difficult to develop EoU for certain patents, the value that can be achieved by asserting or licensing them can far outweigh the costs of analysis. As with any patent evaluation, it is important to understand potential assertion opportunities and revenues: know your market, your competition, and the breadth of use of your innovation before you embark on in-depth analysis.

There are many reasons why you should pursue a patent where EoU may be more difficult to achieve:

  • The economic importance of a patent may be high, giving excellent returns in licensing;
  • The patents available to counter-assert a company may be limited, and EoU needs to be ready for the next technical discussion; and
  • The patents may be the fundamental technology underpinning your company’s products.

In these cases, and others, semiconductor companies have pursed the hard stuff, and have been able to produce additional EoU in their portfolios.

TechInsights’ finding that 14% of the patents for which we have developed EoU were harder to prove means that if you are pursuing these more difficult patents, you are more fully leveraging your semiconductor portfolio.

Martin Bijman is director, IP products at TechInsights, where he is responsible for ensuring customers receive the highest value products and services to help achieve their IP goals. Bijman previously worked at Chipworks for more than ten years. He can be contacted at: mbijman@techinsights.com

 

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